The present invention relates to methods and apparatus for translating address from an external memory space to the memory space of a processor using a simultaneous hardware and software cache fill feature.
In recent years, there has been an insatiable desire for faster computer processing data throughputs because cutting-edge computer applications involve real-time, multimedia functionality. Graphics applications are among those that place the highest demands on a processing system because they require such vast numbers of data accesses, data computations, and data manipulations in relatively short periods of time to achieve desirable visual results. These applications require extremely fast processing speeds, such as many thousands of megabits of data per second. While some processing systems employ a single processor to achieve fast processing speeds, others are implemented utilizing multi-processor architectures. In multi-processor systems, a plurality of sub-processors can operate in parallel (or at least in concert) to achieve desired processing results.
A suitable processing system for executing such applications may include one or more processors and a memory. In some processing systems, it may be desirable to transfer data from an external system (such as another processing system, a CCD or the like) into the memory of the processing system. As the memory space visible to the external system may be translated with respect to the memory space of the processing system, it may be necessary to translate the memory addresses of the external system associated with the transfer of data into the memory of the processing system. It is desirable to make this translation quickly in order to meet speed objective for the processing system.